ST STM32L0x3 User Manual

RM0367 Rev 7 733/1043
RM0367 Inter-integrated circuit (I2C) interface
763
Bus idle detection
A master can assume that the bus is free if it detects that the clock and data signals have
been high for t
IDLE
greater than t
HIGH
,
MAX
. (refer to Table 126: I2C-SMBus specification data
setup and hold times)
This timing parameter covers the condition where a master has been dynamically added to
the bus and may not have detected a state transition on the SMBCLK or SMBDAT lines. In
this case, the master must wait long enough to ensure that a transfer is not currently in
progress. The peripheral supports a hardware bus idle detection.
28.4.13 SMBus initialization
This section is relevant only when SMBus feature is supported. Refer to Section 28.3: I2C
implementation.
In addition to I2C initialization, some other specific initialization must be done in order to
perform SMBus communication:
Received command and data acknowledge control (Slave mode)
A SMBus receiver must be able to NACK each received command or data. In order to allow
ACK control in slave mode, the Slave byte control mode must be enabled by setting the
SBC bit in the I2C_CR1 register. Refer to Slave byte control mode on page 710 for more
details.
Specific address (Slave mode)
The specific SMBus addresses must be enabled if needed. Refer to Bus idle detection on
page 733 for more details.
• The SMBus device default address (0b1100 001) is enabled by setting the SMBDEN
bit in the I2C_CR1 register.
• The SMBus host address (0b0001 000) is enabled by setting the SMBHEN bit in the
I2C_CR1 register.
• The alert response address (0b0001100)
is enabled by setting the ALERTEN bit in the
I2C_CR1 register.
Packet error checking
PEC calculation is enabled by setting the PECEN bit in the I2C_CR1 register. Then the PEC
transfer is managed with the help of a hardware byte counter: NBYTES[7:0] in the I2C_CR2
register. The PECEN bit must be configured before enabling the I2C.
The PEC transfer is managed with the hardware byte counter, so the SBC bit must be set
when interfacing the SMBus in slave mode. The PEC is transferred after NBYTES-1 data
have been transferred when the PECBYTE bit is set and the RELOAD bit is cleared. If
RELOAD is set, PECBYTE has no effect.
Caution: Changing the PECEN configuration is not allowed when the I2C is enabled.

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English