ST STM32L0x3 User Manual

RM0367 Rev 7 859/1043
RM0367 Low-power universal asynchronous receiver transmitter (LPUART)
872
Bit 13 MME: Mute mode enable
This bit activates the mute mode function of the LPUART. When set, the LPUART can switch
between the active and mute modes, as defined by the WAKE bit. It is set and cleared by
software.
0: Receiver in active mode permanently
1: Receiver can switch between mute mode and active mode.
Bit 12 M0: Word length
This bit, with bit 28 (M1) determines the word length. It is set or cleared by software. See Bit
28 (M1) description.
This bit can only be written when the LPUART is disabled (UE=0).
Bit 11 WAKE: Receiver wakeup method
This bit determines the LPUART wakeup method from Mute mode. It is set or cleared by
software.
0: Idle line
1: Address mark
This bit field can only be written when the LPUART is disabled (UE=0).
Bit 10 PCE: Parity control enable
This bit selects the hardware parity control (generation and detection). When the parity
control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit
if M=0) and parity is checked on the received data. This bit is set and cleared by software.
Once it is set, PCE is active after the current byte (in reception and in transmission).
0: Parity control disabled
1: Parity control enabled
This bit field can only be written when the LPUART is disabled (UE=0).
Bit 9 PS: Parity selection
This bit selects the odd or even parity when the parity generation/detection is enabled (PCE
bit set). It is set and cleared by software. The parity will be selected after the current byte.
0: Even parity
1: Odd parity
This bit field can only be written when the LPUART is disabled (UE=0).
Bit 8 PEIE: PE interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register
Bit 7 TXEIE: interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An LPUART interrupt is generated whenever TXE=1 in the LPUART_ISR register
Bit 6 TCIE: Transmission complete interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register
Bit 5 RXNEIE: RXNE interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An LPUART interrupt is generated whenever ORE=1 or RXNE=1 in the LPUART_ISR
register

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English