RM0367 Rev 7 921/1043
RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S)
922
31.7.9 SPI_I
2
S prescaler register (SPI_I2SPR)
Address offset: 0x20
Reset value: 0000 0010 (0x0002)
Bit 3 CKPOL: Steady state clock polarity
0: I
2
S clock steady state is low level
1: I
2
S clock steady state is high level
Note: For correct operation, this bit should be configured when the I
2
S is disabled.
This bit is not used in SPI mode
Bits 2:1 DATLEN: Data length to be transferred
00: 16-bit data length
01: 24-bit data length
10: 32-bit data length
11: Not allowed
Note: For correct operation, these bits should be configured when the I
2
S is disabled.
This bit is not used in SPI mode.
Bit 0 CHLEN: Channel length (number of bits per audio channel)
0: 16-bit wide
1: 32-bit wide
The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to
32-bit by hardware whatever the value filled in. Not used in SPI mode.
Note: For correct operation, this bit should be configured when the I
2
S is disabled.
1514131211109 876543210
Res. Res. Res. Res. Res. Res. MCKOE ODD I2SDIV
rw rw rw
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 MCKOE: Master clock output enable
0: Master clock output is disabled
1: Master clock output is enabled
Note: This bit should be configured when the I
2
S is disabled. It is used only when the I
2
S is in master
mode.
This bit is not used in SPI mode.
Bit 8 ODD: Odd factor for the prescaler
0: real divider value is = I2SDIV *2
1: real divider value is = (I2SDIV * 2)+1
Refer to Section 31.6.4 on page 905. Not used in SPI mode.
Note: This bit should be configured when the I
2
S is disabled. It is used only when the I
2
S is in master
mode.
Bits 7:0 I2SDIV: I2S Linear prescaler
I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values.
Refer to Section 31.6.4 on page 905. Not used in SPI mode.
Note: These bits should be configured when the I
2
S is disabled. It is used only when the I
2
S is in
master mode.
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