RM0367 Rev 7 965/1043
RM0367 Debug support (DBG)
970
33.9.2 Debug support for timers, watchdog and I
2
C
During a breakpoint, it is necessary to choose how the counter of timers and watchdog
should behave:
• They can continue to count inside a breakpoint. This is usually required when a PWM is
controlling a motor, for example.
• They can stop to count inside a breakpoint. This is required for watchdog purposes.
For the I
2
C, the user can choose to block the SMBUS timeout during a breakpoint.
33.9.3 Debug MCU configuration register (DBG_CR)
The DBG_CR register allows to configure the low-power modes when the MCU is under
debug. When one of DBG_CR bits is set, if ULP bit is set in PWR_CR, then FWU bit of
PWR_CR must be set.
It is mapped at address 0x4001 5804.
This register is asynchronously reset by the PORESET (and not the system reset). It can be
written by the debugger under system reset.
If the debugger host does not support these features, it is still possible for the user software
to write to these registers.
Address: 0x04
Only 32-bit access supported
POR Reset: 0x0000 0000 (not reset by system reset)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
DBG_
STAND
BY
DBG_
STOP
DBG_
SLEEP
rw rw rw
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