Debug support (DBG) RM0367
966/1043 RM0367 Rev 7
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 DBG_STANDBY: Debug Standby mode
0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
From software point of view, exiting from Standby is identical than fetching reset vector
(except a few status bit indicated that the MCU is resuming from Standby)
1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and FCLK and
HCLK are provided by the internal RC oscillator which remains active. In addition, the MCU
generate a system reset during Standby mode so that exiting from Standby is identical than
fetching from reset
Bit 1 DBG_STOP: Debug Stop mode
0: (FCLK=Off, HCLK=Off) In Stop mode, the clock controller disables all clocks (including
HCLK and FCLK). When exiting from Stop mode, the clock configuration is identical to the
one after RESET. Consequently, the software must reprogram the clock controller to enable
the PLL, the Xtal, etc.
1: (FCLK=On, HCLK=On) In this case, when entering Stop mode, FCLK and HCLK are
provided by the internal RC oscillator which remains active in Stop mode. When exiting Stop
mode, the software must reprogram the clock controller to enable the PLL, the Xtal, etc. (in
the same way it would do in case of DBG_STOP=0)
Bit 0 DBG_SLEEP: Debug Sleep mode
0: In Sleep mode, FCLK is clocked by the system clock previously configured by the
software while HCLK is disabled. The clock controller configuration is not reset and remains
in its previously programmed state. As a consequence, when exiting from Sleep mode, the
software does not need to reconfigure the clock controller.
1: In this case, when entering in Sleep mode, HCLK is fed by the same clock that is provided
to FCLK (system clock previously configured by the software).
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