RM0367 Rev 7 969/1043
RM0367 Debug support (DBG)
970
33.9.5 Debug MCU APB2 freeze register (DBG_APB2_FZ)
The DBG_APB2_FZ register is used to configure some APB peripheral features when the
MCU is under DEBUG:
• Timer clock counter freeze.
This register is mapped at address 0x4001580C.
It is asynchronously reset by the POR (and not the system reset). It can be written by the
debugger under system reset.
Address: 0x0C
Only 32-bit access is supported.
POR: 0x0000 0000 (not reset by system reset)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
DBG_TIM22_STOP
Res. Res.
DBG_TIM21_STOP
Res. Res.
rw rw
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 DBG_TIM22_STOP: TIM22 counter stopped when core is halted
0: The counter clock of TIM22 is fed even if the core is halted
1: The counter clock of TIM22 is stopped when the core is halted
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 DBG_TIM21_STOP: TIM21 counter stopped when core is halted
0: The counter clock of TIM21 is fed even if the core is halted
1: The counter clock of TIM21 is stopped when the core is halted
Bits 1:0 Reserved, must be kept at reset value.
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