ST STM32L0x3 User Manual

Revision history RM0367
1026/1043 RM0367 Rev 7
04-May-2015
3
(continued)
COMP
Updated Figure 61: Comparator 1 and 2 block diagrams.
Added COMP1LPTIMIN1 in Section 16.5.1: Comparator 1 control and
status register (COMP1_CSR).
Added COMP2LPTIMIN2 and COMP2LPTIMIN1, and updated
COMP2INSEL definition in Section 16.5.2: Comparator 2 control and
status register (COMP2_CSR).
LCD
Updated LCD section to support up t o 52 segments for category 5
devices.
Updated Figure 62: LCD controller block diagram.
Updated Section 17.4.7: COM and SEG multiplexing
RNG:
Replaced PLL48CLK by RNG_CLK.
Added note 1 below Figure 99: RNG block diagram
General-purpose timers (TIM2/3)
Added TIMER3.
Removed 32-bit option.
Updated sequence to use TI2FP2 as trigger 1 in Section 21.3.10:
One-pulse mode.
Added note related to slave timer clock in Section 21.3.15: Timer
synchronization.
Updated MMS bit description in Section 21.4.2: TIMx control register
2 (TIMx_CR2) to add note related to slave timer clock.
Updated SMS bits and Table 97: TIM2/TIM3 internal trigger
connection in Section 21.4.3: TIMx slave mode control register
(TIMx_SMCR) and added note related to slave timer clock.
Removed note related to TIMx_BDTR in OC1M and OC1PE bit
description of Section 21.4.7: TIMx capture/compare mode register 1
(TIMx_CCMR1)/output compare.
Updated ETR_RMP description in Section 21.4.19: TIM2 option
register (TIM2_OR).
General-purpose timers (TIM21/22)
Updated sequence to use TI2FP2 as trigger 1 in Section 22.3.11:
One-pulse mode.
Removed note in IC1F bit description of Section 22.4.7: TIM21/22
capture/compare mode register 1 (TIMx_CCMR1)
Basic timers
Added TIMER7.
Table 181. Document revision history (continued)
Date Revision Changes

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English