ST STM32L0x3 User Manual

RM0367 Rev 7 1027/1043
RM0367 Revision history
1039
04-May-2015
3
(continued)
LPTIM
Updated TRIGSEL description in Section 24.6.4: LPTIM configuration
register (LPTIM_CFGR). Added ext_trig5 in Table 103: LPTIM
external trigger connection.
WWDG:
Updated Figure 203: Watchdog block diagram and timeout formula
and example in Section 26.3.4: How to program the watchdog
timeout.
RTC
Added tamper 3 event for category 5 devices.
Updated WUCKSEL bits in Figure 202: RTC block diagram.
Section 27.4.5: Programmable alarms: Changed MSK0 to MSK1 in
caution note.
I2C
Updated NOSTRECH definition in Section 28.7.1: Control register 1
(I2C_CR1).
USART
Added USART4/5 for category 5 devices. Updated Figure 238:
USART block diagram. Added Low-power modes sections.
Updated Section : Single byte communication.
Updated Table 136: Error calculation for programmed baud rates at
fCK = 32 MHz in both cases of oversampling by 16 or by 8.
Updated Figure 255: IrDA SIR ENDEC- block diagram, Figure 257:
Transmission using DMA and Figure 258: Reception using DMA.
Removed UCESM bit from USARTx_CR3 as well as the capability to
keep enabled USART clock during Stop mode.
Updated REACK flag description in USARTx_ISR register.
LPUART
Updated Figure 263: LPUART block diagram. Added Low-power
modes sections. Removed note in Section 30.4.1: LPUART character
description.
Updated Table 143: Error calculation for programmed baud rates at
fck = 32,768 KHz. Updated Table 148: LPUART interrupt requests.
Changed LPUARTx_RDR and LPUARTx_TDR reset values in Table
149: LPUART register map and reset values. Removed UCESM bit
from LPUART_CR3 as well as the capability to keep enabled
LPUART clock during Stop mode.
SPI
Updated Table 152: Audio-frequency precision using standard 8 MHz
HSE.
Table 181. Document revision history (continued)
Date Revision Changes

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English