Revision history RM0367
1028/1043 RM0367 Rev 7
04-May-2015
3
(continued)
DEBUG
Updated REV_ID bitfield in Section : DBG_IDCODE. Added bits to
support I2C3, TIM3 and TIM7 in Section 33.9.4: Debug MCU APB1
freeze register (DBG_APB1_FZ).
Updated Appendix A: Code examples.
19-Feb-2016 4
Updated Section 2.3: Embedded SRAM.
Flash program memory and data EEPROM
Splitted NVM memory organization table for category 5 devices into 2
tables: NVM organization for UFB = 0 and Flash memory and data
EEPROM remapping.
Updated Table 7: Flash memory and data EEPROM remapping (192
Kbyte category 5 devices) and Table 9: Flash memory and data
EEPROM remapping (128 Kbyte category 5 devices). Updated Table
10: NVM organization for UFB = 0 (64 Kbyte category 5 devices):
BOOT0= 0 and UBS = 1 configuration forbidden.
Replaced bus error by hard fault in the whole section.
Updated Section 3.3.2: Dual-bank boot capability.
Updated description of Level 1 memory read protection in Section
3.4.1: RDP (Read Out Protection).
Updated reset value in Section 3.7.8: Option bytes register
(FLASH_OPTR), Section 3.7.9: Write protection register 1
(FLASH_WRPROT1) and Section 3.7.10: Write protection register 2
(FLASH_WRPROT2).
Updated BFB2 bit description in Section 3.7.8: Option bytes register
(FLASH_OPTR).
Power controller (PWR)
Updated Section 6.2.4: Internal voltage reference (VREFINT) to add
exit from Standby mode on an NRST pulse and note related to LCD
active.
Added note related to HSI16 in Stop mode in Table 32: Summary of
low-power modes.
Updated condition for entering low-power mode in Section 6.3.5:
Entering low-power mode, Table 33: Sleep-now, Table 34: Sleep-on-
exit, Table 35: Sleep-now (Low-power sleep), Table 36: Sleep-on-exit
(Low-power sleep), Table 37: Stop mode and Table 38: Standby
mode.
Updated DS_EE_KOFF and ULP bit definitions in PWR power control
register (PWR_CR).
Table 181. Document revision history (continued)
Date Revision Changes
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