ST STM32L0x3 User Manual

RM0367 Rev 7 1029/1043
RM0367 Revision history
1039
19-Feb-2016
4
(continued)
Reset and clock control (RCC)
Updated Section 7.1.2: Power reset and Figure 16: Simplified
diagram of the reset circuit.
Suppressed EN_VREFINT in Section 7.2.4: HSI48 clock. Updated
Section 7.2.7: LSI clock. Added case of RTC clocked by the LSE in
Section 7.2.12: RTC and LCD clock.. Updated Section 7.2.13:
Watchdog clock
Modified HSI16OUTEN bit definition and HSI16KERON and
HSI16RDYF access type in Section 7.3.1: Clock control register
(RCC_CR). Updated register reset value and HSIDIV6EN bit in
Section 7.3.3: Clock recovery RC register (RCC_CRRCR).
Updated GPIO clock enable in Sleep mode register
(RCC_IOPSMENR), AHB peripheral clock enable in Sleep mode
register (RCC_AHBSMENR), APB2 peripheral clock enable in Sleep
mode register (RCC_APB2SMENR) and APB1 peripheral clock
enable in Sleep mode register (RCC_APB1SMENR) reset values.
System configuration controller (SYSCFG)
Updated UFB bit description in SYSCFG memory remap register
(SYSCFG_CFGR1).
SYSCFG peripheral mode configuration register (SYSCFG_CFGR2):
Updated reset value.
Renamed CAPA bits into LCD_CAPA in SYSCFG_CFGR register and
modified bitfield description.
Removed EN_VERFINT, VREFINT_COMP_RDYF,
VREFINT_ADC_RDYF, SENSOR_ADC_RDYF and
REF_HSI48_RDYF bits in Reference control and status register
(SYSCFG_CFGR3).
Nested vector interrupt controller
Removed MemManage_Handler, BusFault_Handler,Usagefault
_Handler and DebugMon_Handler from Table 53: List of vectors.
Updated EXTI_IMR reset value.
General-purpose I/Os (GPIOs)
Updated OSPEEDy[1:0] definition in Section 9.4.3: GPIO port output
speed register (GPIOx_OSPEEDR) (x = A..E and H).
Analog-to-digital converter (ADC)
Replaced AUTDLY by WAIT in Figure 28: ADC block diagram.
Changed tADC into tCONV.
Updated Section : Analog reference for the ADC internal voltage
regulator. Updated ADC enable sequence in Section 13.4.6: ADC on-
off control (ADEN, ADDIS, ADRDY). Updated Section 13.4.14:
Starting conversions (ADSTART) and ADSTART bit description in
Section 13.15.3: ADC control register (ADC_CR). Updated EOSMP
bit description in Section 13.15.1: ADC interrupt and status register
(ADC_ISR).
Table 181. Document revision history (continued)
Date Revision Changes

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English