RM0367 Rev 7 1037/1043
RM0367 Revision history
1039
06-Dec-2017
6
(continued)
AES hardware accelerator (AES)
General update.
Window watchdog (WWDG)
Updated Figure 208.
Updated Section 26.3.5: Debug mode.
Updated Table 115: WWDG register map and reset values.
Real-time clock (RTC)
Updated Section 27.4.2: GPIOs controlled by the RTC.
Inter-integrated circuit interface (I2C)
Updated OA1[7:1] and OA2[7:1] bit descriptions in Section 28.7.3:
Own address 1 register (I2C_OAR1) and Section 28.7.4: Own
address 2 register (I2C_OAR2), respectively.
Updated NACKCF bit definition in Section 28.7.8: Interrupt clear
register (I2C_ICR).
Universal synchronous asynchronous receiver transmitter
(USART)
Added definition of t
WUUSART
in Section 29.5.5: Tolerance of the
USART receiver to clock deviation.
Restored PSC bit description for Section 29.8.5: USART guard time
and prescaler register (USART_GTPR).
Low-power UART (LPUART)
Added definition of t
WLPUART
in Section 30.4.5: Tolerance of the
LPUART receiver to clock deviation.
Added Note in Section 30.4.11: Wakeup from Stop mode using
LPUART.
Note related to 7-bit data length removed in Section 30.7.1: Control
register 1 (LPUART_CR1).
Debug
Updated Cortex-M0+ ID code in Section 33.5.3: SW-DP state
machine (reset, idle states, ID code) and Section 33.5.5: SW-DP
registers.
Updated Appendix A.3.10: Program half-page to Flash program
memory code example and A.8.1: Calibration code example.
Table 181. Document revision history (continued)
Date Revision Changes
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