ST STM32L0x3

Revision history RM0367
1038/1043 RM0367 Rev 7
05-Apr-2021 7
Updated cover introduction and related documents.
Document conventions
Added Section 1.1: General information.
Updated Section 1.2: List of abbreviations for registers.
Removed note related to product under development in Table 1:
STM32L0x3 memory density.
Flash program memory and data EEPROM (FLASH)
Updated information about granularity of EEPROM and Flash in:
– Section 3.2: NVM main features.
– Section 3.3.1: NVM organization.
– Section 3.3.4: Writing/erasing the NVM ‘Program half-page in Flash
program memory’ and ‘Detailed description of NVM write/erase
operations’ paragraphs.
Liquid crystal display controller (LCD)
Updated Table 76: VLCDrail connections to GPIO pins.
Power control (PWR)
Updated:
– Section 6.1.1: Independent A/D and DAC converter supply and
reference voltage.
– Section 6.3.9: Stop mode ‘Entering Stop mode’ paragraph.
– Section 6.4.1: PWR power control register (PWR_CR) DBP bit
description adding note.
– ‘power voltage control’ by ‘programmable voltage control’.
Reset and clock control (RCC)
Updated:
– Figure 16: Simplified diagram of the reset circuit.
– Section 7.3.5: Clock interrupt enable register (RCC_CIER) bits in
read/write.
– Section 7.3.21: Control/status register (RCC_CSR) RTCSEL[1:0]
bits description.
System configuration controller (SYSCFG)
Updated:
– Section 10.2.2: SYSCFG peripheral mode configuration register
(SYSCFG_CFGR2) LCD_CAPA[4:0] bits description.
– Section 10.2.3: Reference control and status register
(SYSCFG_CFGR3) EN_VREFINT bit description.
Extended interrupt and event controller (EXTI)
Updated Section 13.5.7: EXTI register map.
Table 181. Document revision history (continued)
Date Revision Changes