ST STM32L0x3

RM0367 Rev 7 203/1043
RM0367 Reset and clock control (RCC)
225
Bit 17 USART2RST: USART2 reset
This bit is set and cleared by software.
0: No effect
1: Resets USART2
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2RST: SPI2 reset
This bit is set and cleared by software.
0: No effect
1: Resets SPI2
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGRST: Window watchdog reset
This bit is set and cleared by software.
0: No effect
1: Resets window watchdog
Bit 10 Reserved, must be kept at reset value.
Bit 9 LCDRST: LCD reset
This bit is set and cleared by software.
0: No effect
1: Resets LCD
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 TIM7RST: Timer 7 reset
Set and cleared by software.
0: No effect
1: Resets timer7
Bit 4 TIM6RST: Timer 6 reset
Set and cleared by software.
0: No effect
1: Resets timer6
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM3RST: Timer3 reset
Set and cleared by software.
0: No effect
1: Resets timer3
Bit 0 TIM2RST: Timer2 reset
Set and cleared by software.
0: No effect
1: Resets timer2