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RM0367 Rev 7 665/1043

RM0367 Real-time clock (RTC)

694

Note: TSF is set 2 ck_apre cycles after the time-stamp event occurs due to synchronization

process.

There is no delay in the setting of TSOVF. This means that if two time-stamp events are

close together, TSOVF can be seen as '1' while TSF is still '0'. As a consequence, it is

recommended to poll TSOVF only after TSF has been set.

Caution: If a time-stamp event occurs immediately after the TSF bit is supposed to be cleared, then

both TSF and TSOVF bits are set.To avoid masking a time-stamp event occurring at the

same moment, the application must not write ‘0’ into TSF bit unless it has already read it to

‘1’.

Optionally, a tamper event can cause a time-stamp to be recorded. See the description of

the TAMPTS control bit in Section 27.7.16: RTC tamper configuration register

(RTC_TAMPCR).

27.4.14 Tamper detection

The RTC_TAMPx input events can be configured either for edge detection, or for level

detection with filtering.

The tamper detection can be configured for the following purposes:

• erase the RTC backup registers (default configuration)

• generate an interrupt, capable to wakeup from Stop and Standby modes

• generate a hardware trigger for the low-power timers

RTC backup registers

The backup registers (RTC_BKPxR) are not reset by system reset or when the device

wakes up from Standby mode.

The backup registers are reset when a tamper detection event occurs (see Section 27.7.20:

RTC backup registers (RTC_BKPxR) and Tamper detection initialization on page 665)

except if the TAMPxNOERASE bit is set, or if TAMPxMF is set in the RTC_TAMPCR

Tamper detection initialization

Each input can be enabled by setting the corresponding TAMPxE bits to 1 in the

RTC_TAMPCR register.

Each RTC_TAMPx tamper detection input is associated with a flag TAMPxF in the RTC_ISR

When TAMPxMF is cleared:

The TAMPxF flag is asserted after the tamper event on the pin, with the latency provided

below:

• 3 ck_apre cycles when TAMPFLT differs from 0x0 (Level detection with filtering)

• 3 ck_apre cycles when TAMPTS=1 (Timestamp on tamper event)

• No latency when TAMPFLT=0x0 (Edge detection) and TAMPTS=0

A new tamper occurring on the same pin during this period and as long as TAMPxF is set

cannot be detected.

When TAMPxMF is set:

ST STM32L0x3 User Manual

Questions and Answers: