Flash program memory and data EEPROM (FLASH) RM0367
74/1043 RM0367 Rev 7
Change the CPU Frequency
After reset, the clock used is the MSI (2.1 MHz) and 0 wait state is configured in the
FLASH_ACR register. The following software sequences have to be respected to tune the
number of wait states needed to access the NVM with the CPU frequency.
A CPU clock or a number of wait state configuration changes may take some time before
being effective. Checking the AHB prescaler factor and the clock source status values is a
way to ensure that the correct CPU clock frequency is the configured one. Similarly, the read
of FLASH_ACR is a way to ensure that the number of programmed wait states is effective.
Increasing the CPU frequency (in the same voltage range)
1. Program 1 wait state in LATENCY bit of FLASH_ACR register, if necessary.
2. Check that the new number of wait states is taken into account by reading the
FLASH_ACR register. When the number of wait states changes, the memory interface
modifies the way the read access is done to the NVM. The number of wait states
cannot be modified when a read operation is ongoing, so the memory interface waits
until no read is done on the NVM. If the master reads back the content of the
FLASH_ACR register, this reading is stopped (and also the master which requested
the reading) until the number of wait states is really changed. If the user does not read
back the register, the following access to the NVM may be done with 0 wait states,
even if the clock frequency has been increased, and consequently the values are
wrong.
3. Modify the CPU clock source and/or the AHB clock prescaler in the Reset & Clock
Controller (RCC).
4. Check that the new CPU clock source and/or the new CPU clock prescaler value is
taken into account by reading respectively the clock source status and/or the AHB
prescaler value in the Reset & Clock Controller (RCC). This check is important as some
clocks may take time to get available.
For code example, refer to A.2.1: Increasing the CPU frequency preparation sequence
code, A.2.3: Switch from PLL to HSI16 sequence code and A.2.4: Switch to PLL sequence
code.
Decreasing the CPU frequency (in the same voltage range)
1. Modify the CPU clock source and/or the AHB clock prescaler in the Reset & Clock
Controller (RCC).
2. Check that the new CPU clock source and/or the new CPU clock prescaler value is
taken into account by reading respectively the clock source status and/or the AHB
prescaler value in the Reset and Clock Controller (RCC).
3. Program 0 wait state in LATENCY bit of the FLASH_ACR register, if needed.
4. Check that the new number of wait states is taken into account by reading
FLASH_ACR. It is necessary to read back the register for the reasons explained in the
previous paragraph.
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