RM0367 Rev 7 973/1043
RM0367 Code examples
1020
Appendix A Code examples
A.1 Introduction
This appendix shows the code examples of the sequence described in this Reference
Manual.
These code examples are extracted from the STM32L0xx Snippet firmware package
STM32SnippetsL0 available on www.st.com.
These code examples used the peripheral bit and register description from the CMSIS
header file (stm32l0xx.h).
Code lines starting with // should be uncommented if the given register has been modified
before.
A.2 NVM/RCC Operation code example
A.2.1 Increasing the CPU frequency preparation sequence code
/* (1) Set one wait state in Latency bit of FLASH_ACR */
/* (2) Check the latency is set */
/* (3) Switch the clock on HSI16/4 and disable PLL */
/* (4) Set PLLMUL to 16 to get 32MHz on CPU clock */
/* (5) Enable and switch on PLL */
FLASH->ACR |= FLASH_ACR_LATENCY; /* (1) */
while ((FLASH->ACR & FLASH_ACR_LATENCY) == 0); /* (2) */
SwitchFromPLLtoHSI(); /* (3) */
RCC->CFGR = (RCC->CFGR & (~(uint32_t)RCC_CFGR_PLLMUL))
| RCC_CFGR_PLLMUL16; /* (4) */
SwitchOnPLL(); /* (5) */
A.2.2 Decreasing the CPU frequency preparation sequence code
/* (1) Switch the clock on HSI16/4 and disable PLL */
/* (2) Set PLLMUL to 4 to get 8MHz on CPU clock */
/* (3) Enable and switch on PLL */
/* (4) Set one wait state in Latency bit of FLASH_ACR */
/* (5) Check the latency is set */
SwitchFromPLLtoHSI(); /* (1) */
RCC->CFGR = (RCC->CFGR & (~(uint32_t)RCC_CFGR_PLLMUL))
| RCC_CFGR_PLLMUL4; /* (2) */
SwitchOnPLL(); /* (3) */
FLASH->ACR &= ~FLASH_ACR_LATENCY; /* (4) */
while ((FLASH->ACR & FLASH_ACR_LATENCY) != 0); /* (5) */
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