RM0367 Rev 7 1033/1043
RM0367 Revision history
1039
14-Nov-2016 5
Flash program memory and data EEPROM
In Section 3.4.1: RDP (Read Out Protection), for protection level 2,
added note related to debug feature disabled under reset.
FIREWALL
Updated LENG bitfield description in Section 5.4.6: Volatile data
segment length (FW_VDSL).
Power control (PWR)
Updated voltage regulator status in Stop mode in Table 32: Summary
of low-power modes.
Updated power consumption methods in Stop mode in Section :
Entering Stop mode.
Updated PDDS bit description in Section 6.4.1: PWR power control
register (PWR_CR).
Reset and clock control (RCC)
HSE RTC clock source frequency changed to 4 MHz.
Section 7.1.2: Power reset: added internal pull-up deactivation in
case of internal reset and updated Figure 16: Simplified diagram of
the reset circuit.
Updated Section 7.2.11: LSE Clock Security System to add condition
on LSE oscillator minimum frequency.
System configuration controller (SYSCFG)
Updated Reference control and status register (SYSCFG_CFGR3):
Added EN_VREFINT
Renamed ENBUF_VREFINT_COMP into
ENBUF_VREFINT_COMP2 and description updated.
Updated ENBUF_SENSOR_ADC and ENBUF_VREFINT_ADC
DMA controller (DMA)
Removed DMA_REQx from Figure 28: DMA request mapping.
Analog-to-digital converter (ADC)
Replaced ADVREFEN by ADVREGEN in Section : Analog reference
for the ADC internal voltage regulator.
Updated calibration software procedure in Section 14.4.2: Calibration
(ADCAL).
Changed EXTEN value from 00 to 01 in the note related to HW trigger
selection in Section 13.4.14: Starting conversions (ADSTART).
Comparator (COMP)
Updated COMPx_CSR to add a note related to VREFINT in
COMP2INNSEL bit description.
Table 181. Document revision history (continued)
Date Revision Changes
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