ARM ARM1176JZF-S User Manual

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ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-30
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2.11 Additional instructions
To support extensions to ARMv6, the ARM1176JZF-S processor includes these instructions in
addition to those in the ARMv6 and TrustZone architectures:
• Load Register Exclusive instructions, see LDREXB, LDREXH on page 2-31, and
LDREXD on page 2-33
• Store Register Exclusive instructions, see STREXB, STREXH on page 2-32, and STREXH
on page 2-32
• Clear Register Exclusive instruction, see CLREX on page 2-34
• Yield instruction, see NOP-compatible hints on page 2-34.
2.11.1 Load or Store Byte Exclusive
These instruction operate on unsigned data of size byte.
No alignment restrictions apply to the addresses of these instructions.
The LDREXB and STREXB instructions share the same data monitors as the LDREX and
STREX instructions, a local and a global monitor for each processor, for shared memory
support.
LDREXB
Figure 2-11 shows the format of the Load Register Byte Exclusive, LDREXB, instruction.
Figure 2-11 LDREXB instruction
Syntax
LDREXB{<cond>} <Rxf>, [<Rbase>]
Operation
if ConditionPassed(cond) then
processor_id = ExecutingProcessor()
Rd = Memory[Rn,1]
if Shared(Rn) ==1 then
physical_address=TLB(Rn)
MarkExclusiveGlobal(physical_address,processor_id,1)
MarkExclusiveLocal(processor_id)
STREXB
Figure 2-12 shows the format of the Store Register Byte Exclusive, STREXB, instruction.
Figure 2-12 STREXB instructions
Syntax
STREXB{<cond>} <Rd>, <Rm>, [<Rn>]]
SBOCond
31 28 27 21 20 19 15 12 11 7 4 3 0
0 0 0 1 1 1 0 1 Rn Rd SBO 1 0 0 1
16 8
RmCond
31 28 27 21 20 19 15 12 11 7 4 3 0
0 0 0 1 1 1 0 0 Rn Rd SBO 1 0 0 1
16 8

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English