ARM ARM1176JZF-S User Manual

Level Two Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-29
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An STM2 to word 7 is split into two operations as shown in Table 8-49.
8.5.26 Cacheable Write-Through or Noncacheable STM3
Table 8-50 shows the values of AWADDRRW, AWBURSTRW, AWSIZERW, and
AWLENRW for STM3s to words 0 to 5 over the Data Read/Write Interface.
An STM3 to word 6 or 7 is split into two operations as shown in Table 8-51.
Table 8-48 Cacheable Write-Through or Noncacheable STRD or STM2 to words 0, 1, 2, 3, 4, 5, or 6
Address[4:0]
AWADDRR
W
AWBURSTR
W
AWSIZERW AWLENRW First WSTRBRW
0x00 , word 0 0x00 Incr 64-bit 1 data transfer b1111 1111
0x04 , word 1 0x04 Incr 32-bit 2 data transfers b1111 0000
0x08 , word 2 0x08 Incr 64-bit 1 data transfer b1111 1111
0x0C , word 3 0x0C Incr 32-bit 2 data transfers b1111 0000
0x10 , word 4 0x10 Incr 64-bit 1 data transfer b1111 1111
0x14 , word 5 0x14 Incr 32-bit 2 data transfers b1111 0000
0x18 , word 6 0x18 Incr 64-bit 1 data transfer b1111 1111
Table 8-49 Cacheable Write-Through or Noncacheable STM2 to word 7
Address[4:0] Operations
0x1C STR to 0x1C + STR to 0x00
Table 8-50 Cacheable Write-Through or Noncacheable STM3 to words 0, 1, 2, 3, 4, or 5
Address[4:0]
AWADDRR
W
AWBURSTR
W
AWSIZERW AWLENRW First WSTRBRW
0x00 , word 0 0x00 Incr 32-bit 3 data transfers b0000 1111
0x04 , word 1 0x04 Incr 32-bit 3 data transfers b1111 0000
0x08 , word 2 0x08 Incr 32-bit 3 data transfers b0000 1111
0x0C , word 3 0x0C Incr 32-bit 3 data transfers b1111 0000
0x10 , word 4 0x10 Incr 32-bit 3 data transfers b0000 1111
0x14 , word 5 0x14 Incr 32-bit 3 data transfers b1111 0000
Table 8-51 Cacheable Write-Through or Noncacheable STM3 to words 6 or 7
Address[4:0] Operations
0x18 , word 6 STM2 to 0x18 + STR to 0x00
0x1C
, word 7 STR to 0x1C + STM2 to 0x00

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English