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Memory Management Unit

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6.6 Memory region attributes

Each TLB entry has an associated set of memory region attributes. These control:

• accesses to the caches

• how the write buffer is used

• if the memory region is shareable

• if the targeted memory is Secure or not.

6.6.1 C and B bit, and type extension field encodings

The ARMv6 MMU architecture originally defined five bits to describe all of the options for

inner and outer cachability. These five bits, the Type Extension Field, TEX[2:0], Cacheable, C,

and Bufferable, B bits, are set in the descriptors.

Few application make use of all these options simultaneously. For this reason, a new

configuration bit, TEX remap, bit [28] in the CP15 Control Register, permits the core to support

a smaller number of options by using only the TEX[0], C and B bits.

The OS can configure this subset of options through a remap mechanism for these TEX[0], C,

and B bits. The TEX[2:1] bits in the descriptor then become 2 OS managed page table bits.

Additionally, certain page tables contain the Shared bit, S, used to determine if the memory

region is Shared or not. If not present in the descriptor, the Shared bit is assumed to be 0,

Non-Shared. In the TexRemap=1 configuration, the Shared bit can be remapped too.

For TrustZone support, the TEX remap bit is duplicated as Secure and Non-secure versions, so

it is possible to configure in each world the options that are available to the core.

The TLB does not cache the effect of the TEX remap bit on page tables. As a result, there is no

requirement for the processor to invalidate the TLB on a change of the TEX remap bit to rely on

the effect of those changes taking place.

Note

The terms Inner and Outer in this document represent the levels of caches that can be built in a

system. Inner refers to the innermost caches, including level one. Outer refers to the outermost

caches. The boundary between Inner and Outer caches is defined in the implementation of a

cached system. Inner must always include level one. In a system with three levels of caches, an

example is for the Inner attributes to apply to level one and level two, while the Outer attributes

apply to level three. In a two-level system, it is envisaged that Inner always applies to level one

and Outer to level two.

In the processor, Inner refers to level one and the ARSIDEBAND[4:1], for read, and

AWSIDEBAND[4:1], for writes, signals show the Inner Cacheable values.

ARCACHE, for reads, and AWCACHE, for writes, show the Outer Cacheable properties.

TexRemap=0 configuration

This is the standard ARMv6 configuration. The five TEX[2:0], C, and B bits are used to encode

the memory region type. For page tables formats with no TEX field, you must use the value

3'b000.

ARM ARM1176JZF-S User Manual

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