System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-97
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Accesses to the TCM Region Registers and TCM Non-secure Control Access Registers in the
Secure world, access the bank of CP15 registers related to TCM configuration selected by the
Secure TCM Selection Register. Accesses to the TCM Region Registers in the Non-secure
world, access the bank of CP15 registers related to TCM configuration selected by the
Non-secure TCM Selection Register.
Table 3-94 lists the results of attempted access for each mode.
To use the TCM Selection Register read or write CP15 c9 with:
• Opcode_1 set to 0
• CRn set to c9
• CRm set to c2
• Opcode_2 set to 0.
For example:
MRC p15,0,<Rd>,c9,c2,0 ; Read TCM Selection register
MCR p15,0,<Rd>,c9,c2,0 ; Write TCM Selection register
3.2.30 c9, Cache Behavior Override Register
The purpose of the Cache Behavior Override Register is to control cache write through and line
fill behavior for interruptible cache operations, or during debug. The register enables you to
ensure that the contents of caches do not change, for example in debug.
The Cache Behavior Override Register is:
•in CP15 c9
• a 32 bit read/write register, Table 3-95 on page 3-98 lists the access for each bit in Secure
and Non-secure worlds
• accessible in privileged modes only.
Figure 3-55 shows the bit arrangement for the Cache Behavior Override Register.
Figure 3-55 Cache Behavior Override Register format
Table 3-94 Results of access to the TCM Selection Register
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Secure data Secure data Non-secure data Non-secure data Undefined exception
31 6543210
SBZ
S_WT
S_IL
S_DL
NS_WT
NS_IL
NS_DL
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