ARM ARM1176JZF-S User Manual

Level Two Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-31
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8.5.29 Cacheable Write-Through or Noncacheable STM6
Table 8-56 shows the values of AWADDRRW, AWBURSTRW, AWSIZERW, and
AWLENRW for STM6s to words 0 to 2 over the Data Read/Write Interface.
An STM6 to words 3 to 7 is split into two operations as shown in Table 8-57.
8.5.30 Cacheable Write-Through or Noncacheable STM7
Table 8-58 shows the values of AWADDRRW, AWBURSTRW, AWSIZERW, and
AWLENRW for STM7s to words 0 or 1 over the Data Read/Write Interface.
An STM7 to words 2 to 7 is split into two operations as shown in Table 8-59 on page 8-32.
0x14 , word 5 STM3 to 0x14 + STM2 to 0x00
0x18
, word 6 STM2 to 0x18 + STM3 to 0x00
0x1C
, word 7 STR to 0x1C + STM4 to 0x00
Table 8-55 Cacheable Write-Through or Noncacheable STM5 to word 4, 5, 6, or 7
Address[4:0] Operations
Table 8-56 Cacheable Write-Through or Noncacheable STM6 to word 0, 1, or 2
Address[4:0]
AWADDRR
W
AWBURSTR
W
AWSIZERW AWLENRW First WSTRBRW
0x00 , word 0 0x00 Incr 64-bit 3 data transfers b1111 1111
0x04 , word 1 0x04 Incr 32-bit 6 data transfers b1111 0000
0x08 , word 2 0x08 Incr 64-bit 3 data transfers b1111 1111
Table 8-57 Cacheable Write-Through or Noncacheable STM6 to word 3, 4, 5, 6, or 7
Address[4:0] Operations
0x0C , word 3 STM5 to 0x0C + STR to 0x00
0x10
, word 4 STM4 to 0x10 + STM2 to 0x00
0x14
, word 5 STM3 to 0x14 + STM3 to 0x00
0x18
, word 6 STM2 to 0x18 + STM4 to 0x00
0x1C
, word 7 STR to 0x1C + STM5 to 0x00
Table 8-58 Cacheable Write-Through or Noncacheable STM7 to word 0 or 1
Address[4:0]
AWADDRR
W
AWBURSTR
W
AWSIZERW AWLENRW First WSTRBRW
0x00 , word 0 0x00 Incr 32-bit 7 data transfers b0000 1111
0x04 , word 1 0x04 Incr 32-bit 7 data transfers b1111 0000

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English