Cycle Timings and Interlock Behavior
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-17
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Table 16-14 lists the cycle timing behavior for loads to the PC.
Only cycle times for aligned accesses are given because Unaligned accesses to the PC are not
supported.
The processor includes a three-entry return stack that can predict procedure returns. Any load
to the pc with an immediate offset, and the stack pointer R13 as the base register is considered
a procedure return.
For condition code failing cycle counts, you must use the cycles for the non-PC destination
variants.
Table 16-15 lists the explanation of
<addr_md_1cycle>
and
<addr_md_2cycle>
that Table 16-13 on
page 16-16 and Table 16-14 use.
Table 16-14 Cycle timing behavior for loads to the PC
Example instruction
Cycle
s
Memory cycles Result latency Comments
LDR pc, [sp, #cns] (!)
4 1 - Correctly return stack predicted
LDR pc, [sp], #cns
4 1 - Correctly return stack predicted
LDR pc, [sp, #cns] (!)
9 1 - Return stack mispredicted
LDR pc, [sp], #cns
9 1 - Return stack mispredicted
LDR <cond> pc, [sp, #cns] (!)
8 1 - Conditional return, or empty
return stack
LDR <cond> pc, [sp], #cn
s 8 1 - Conditional return, or empty
return stack
LDR pc, <addr_md_1cycle>
a
81 - -
LDR pc, <addr_md_2cycle>
a
92 - -
a. Table 16-15 for an explanation of
<addr_md_1cycle>
and
<addr_md_2cycle>
.
T
able
16-15 <addr_md_1
cycle> and <addr_md
_2cycle> LDR
example instruction
explanation
Example instruction Early Reg Comment
<addr_md_1cycle>
LDR <Rd>, [<Rn>, #cns] (!) <Rn>
If an immediate offset, or a positive register offset with no
shift or shift LSL #2, then one-issue cycle.
LDR <Rd>, [<Rn>, <Rm>] (!) <Rn>, <Rm>
LDR <Rd>, [<Rn>, <Rm>, LSL #2] (!) <Rn>, <Rm>
LDR <Rd>, [<Rn>], #cns <Rn>
LDR <Rd>, [<Rn>], <Rm> <Rn>, <Rm>
LDR <Rd>, [<Rn>], <Rm>, LSL #2 <Rn>, <Rm>
<addr_md_2cycle>
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