Debug
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13.3 Debug registers
Table 13-1 lists definitions of terms used in register descriptions.
On a power-on reset, all the CP14 debug registers take the values indicated by the Reset value
column in the register bit field definition tables:
• Table 13-4 on page 13-8
• Table 13-6 on page 13-14
• Table 13-11 on page 13-18
• Table 13-14 on page 13-21
• Table 13-16 on page 13-21.
In these tables, - means an Undefined Reset value.
13.3.1 Accessing debug registers
To access the CP14 debug registers you must set Opcode_1 and CRn to 0. The Opcode_2 and
CRm fields of the coprocessor instructions are used to encode the CP14 debug register number,
where the register number is
{<Opcode2>, <CRm>}
.
Table 13-2 lists the CP14 debug register map. All of these registers are also accessible as scan
chains from the DBGTAP.
Table 13-1 Terms used in register descriptions
Term Description
R Read-only. Written values are ignored. However, it is written as 0 or preserved by writing the same value
previously read from the same fields on the same processor.
W Write-only. This bit cannot be read. Reads return an Unpredictable value.
RW Read or write.
C Cleared on read. This bit is cleared whenever the register is read.
UNP/SBZP Unpredictable or Should Be Zero or Preserved (SBZP). A read to this bit returns an Unpredictable value.
It is written as 0 or preserved by writing the same value previously read from the same fields on the same
processor. These bits are usually reserved for future expansion.
Core view This column defines the core access permission for a given bit.
External view This column defines the DBGTAP debugger view of a given bit.
Read/write
attributes
This is used when the core and the DBGTAP debugger view are the same.
Table 13-2 CP14 debug register map
Binary address
Register
number
CP14 debug register name Abbreviation
Opcode_2 CRm
b000 b0000 c0 Debug ID Register DIDR
b000 b0001 c1 Debug Status and Control Register DSCR
b000 b0010-b0100 c2-c4 Reserved -
b000 b0101 c5 Data Transfer Register DTR
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