Level Two Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-6
ID012310 Non-Confidential, Unrestricted Access
8.2 Synchronization primitives
On previous architectures support for shared memory synchronization has been with the
read-locked-write operations that swap register contents with memory, the SWP and SWPB
instructions. These support basic busy and free semaphore mechanisms. For details of the swap
instructions, and how to use them to implement semaphores, see the ARM Architecture
Reference Manual.
ARMv6 and its extensions introduce support for more comprehensive shared-memory
synchronization primitives that scale for multiple-processor system designs. Two sets of
instructions are introduced that support multiple-processor and shared-memory inter-process
communication:
• load-exclusive, LDREX, LDREXB, LDREXH, and LDREXD
• store-exclusive, STREX, STREXB, STREXH, and STREXD.
The exclusive-access instructions rely on the ability to tag a physical address as exclusive-access
for a particular processor. This tag is later used to determine if an exclusive store to an address
occurs.
For non-shared memory regions, the LDREX{B,H,D} and STREX{B,H,D} instructions are
presented to the ports as normal LDR or STR. If a processor does an STR on a memory region
that it has already marked as exclusive, this does not clear the tag. However, if the region has
been marked by another processor, an STR clears the tag.
Other events might cause the tag to be cleared. In particular, for memory regions that are not
shared, it is systems dependent whether a store by another processor to a tagged physical address
causes the tag to be cleared.
An external abort on either a load-exclusive or store-exclusive puts the processor into Abort
mode.
For an exclusive read access, the processor considers any response apart from EXOKAY as an
external abort.
For an exclusive write access, the processor considers any error response as an external abort,
an OKAY response sets the returned status value to 1.
For SWP and SWPB instructions, in the case of an error response on the locked read access and
to unlock the bus, the processor performs a dummy normal write access with all byte strobes
disabled at the same address as the locked read access.
Note
An external abort on a load-exclusive can leave the processor internal monitor in its exclusive
state and might affect your software. If it does you must execute a CLREX instruction in your
abort handler to clear the processor internal monitor to an open state.
8.2.1 Load-exclusive instruction
Load-exclusive performs a load from memory and causes the physical address of the access to
be tagged as exclusive-access for the requesting processor. This causes any other physical
address that has been tagged by the requesting processor to no longer be tagged as
exclusive-access.
To Next Page
Loading...
Need help?
General
