ARM ARM1176JZF-S - Table 3-143 Results of Access to the System Validation Counter Register; Figure 3-74 System Validation Counter Register Format for External Debug Request Counter

System Control Coprocessor
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Figure 3-74 System Validation Counter Register format for external debug request counter
Table 3-143 lists the results of attempted access for each mode. Access in Secure User mode and
in the Non-secure world depends on the V bit, see c15, Secure User and Non-secure Access
Validation Control Register on page 3-132.
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
To use the System Validation Counter Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c15
• CRm set to c12
• Opcode_2 set to:
— 1, Read/write reset counter
— 2, Read/write interrupt counter
— 3, Read/write fast interrupt counter
— 7, Write external debug request counter.
For example:
MRC p15, 0, <Rd>, c15, c12, 1 ;Read reset counter
MCR p15, 0, <Rd>, c15, c12, 1 ;Write reset counter
MRC p15, 0, <Rd>, c15, c12, 2 ;Read interrupt counter
MCR p15, 0, <Rd>, c15, c12, 2 ;Write interrupt counter
MRC p15, 0, <Rd>, c15, c12, 3 ;Read fast interrupt counter
MCR p15, 0, <Rd>, c15, c12, 3 ;Write fast interrupt counter
MCR p15, 0, <Rd>, c15, c12, 7 ;Write external debug request counter
A read or write to the System Validation Counter Register with a value of Opcode_2 other than
1, 2, 3, or 7 has no effect.
When the system starts the counters they count up, incrementing by one on each core clock
cycle, until they wrap around. When the counters wrap around they cause the specified event to
occur. See c15, System Validation Operations Register on page 3-142.
SBZ/UNP
31 65 0
Counter value
Table 3-143 Results of access to the System Validation Counter Register
Function
V
bit
Secure Privileged Non-secure Privileged User
Read Write Read Write Read Write
Reset, interrupt, and
fast interrupt counters
0 Data Data Undefined
exception
Undefined
exception
Undefined
exception
Undefined
exception
1 Data Data Data Data Data Data
External debug request
counter
0 Unpredictable Data Undefined
exception
Undefined
exception
Undefined
exception
Undefined
exception
1 Unpredictable Data Unpredictable Data Unpredictable Data