ARM ARM1176JZF-S - Figure 6-4 Backwards-Compatible First-Level Descriptor Format

Memory Management Unit
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For both level 1 and level 2 page table walks, the processor performs external accesses with
Secure or Non-secure rights depending on the Secure or Non-secure state of the MMU request
that causes the page table walk. This ensures that Secure translation table descriptors are always
fetched from a Secure memory, and that Non-secure translation table descriptors are always
fetched from Non-secure memory.
6.11.1 Backwards-compatible page table translation subpage AP bits enabled
When the CP15 Control Register c1 bit 23 is set to 0, the subpage AP bits are enabled and the
page table formats are backwards-compatible with ARMv4 and ARMv5 MMU architectures.
This bit is duplicated as Secure and Non-secure versions so that the system can enable or disable
subpages independently in each world.
All mappings are treated as global, and executable, XN = 0. All Normal memory is Non-Shared.
Device memory can be Shared or Non-Shared as determined by the TEX bits and the C and B
bits. For large and small pages, there can be four subpages defined with different access
permissions. For a large page, the subpage size is 16KB and is accessed using bits [15:14] of the
page index of the virtual address. For a small page, the subpage size is 1KB and is accessed
using bits [11:10] of the page index of the virtual address.
The use of subpage AP bits where AP3, AP2, AP1, and AP0 contain different values is
deprecated.
Backwards-compatible page table format
Figure 6-4 shows a backwards-compatible format first-level descriptor.
Figure 6-4 Backwards-compatible first-level descriptor format
If the P bit is supported and set for the memory region, it indicates to the system memory
controller that this memory region has ECC enabled. ARM1176JZF-S processors do not support
the P bit.
When bits [1:0] of the first-level descriptor are b01, the descriptor points to a second-level page
table, called a Coarse page table. Figure 6-5 on page 6-38 shows a backwards-compatible
format second-level descriptors.
1
N
S
SBZ
0
SBZ
N
S
N
S
S
B
Z
S
B
Z
TEX
1Coarse page table base address P Domain 0
0Ignored
31 20 19 12 11 10 9 8 5 4 3 2 1 0
0
0Section base address AP P Domain 0 C B 1
11
Translation fault
Coarse page table
Section (1MB)
15 14
Reserved
TEX
0
Supersection base
address
SBZ AP P Ignored 0 C B 1
Supersection
(16MB)
18 172324