ARM ARM1176JZF-S - Table 20-9 Media and VFP Feature Register 0 Bit Functions; Figure 20-8 Media and VFP Feature Register 0 Format

VFP Programmer’s Model
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20.4.5 Media and VFP Feature Register 0
The purpose of the Media and VFP Feature Register 0 is to provide information about the
features that the VFP unit contains.
Media and VFP Feature Register 0 is:
• a 32-bit read-only register
• accessible in any mode when the VFP is enabled by the EN bit, see Floating-point
exception register, FPEXC on page 20-16
• accessible only in Privileged modes when the VFP is disabled by the EN bit.
Figure 20-8 shows the bit arrangement for Media and VFP Feature Register 0.
Figure 20-8 Media and VFP Feature Register 0 format
Table 20-9 shows how the bit values correspond with the Media and VFP Feature Register 0
functions.
The values in the Media and VFP Feature Register 0 are implementation defined.
---- -
31 16 15 8 7 3 0
- - -
Table 20-9 Media and VFP Feature Register 0 bit functions
Bits Name Function
[31:28] - Indicates the VFP hardware support level when user traps are disabled.
0x1 , In ARM1176JZF-S processors when Flush-to-Zero and Default_NaN and Round-to-Nearest are
all selected in FPSCR, the coprocessor does not require support code. Otherwise floating point
support code is required.
[27:24] - Indicates support for short vectors.
0x1 , ARM1176JZF-S processors support short vectors.
[23:20] - Indicates support for hardware square root.
0x1 , ARM1176JZF-S processors support hardware square root.
[19:16] - Indicates support for hardware divide.
0x1 , ARM1176JZF-S processors support hardware divide.
[15:12] - Indicates support for user traps.
0x1 , ARM1176JZF-S processors support software traps, support code is required.
[11:8] - Indicates support for double precision VFP.
0x1 , ARM1176JZF-S processors support v2.
[7:4] - Indicates support for single precision VFP.
0x1 , ARM1176JZF-S processors support v2.
[3:0] - Indicates support for the media register bank.
0x1 , ARM1176JZF-S processors support 16, 64-bit registers.