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ARM ARM1176JZF-S - Table 3-106 Results of Access to the DMA Identification and Status Registers

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System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-107
ID012310 Non-Confidential, Unrestricted Access
Access in the Non-secure world depends on the DMA bit, see c1, Non-Secure Access Control
Register on page 3-55. The processor can only access these registers in Privileged modes.
Table 3-106 lists the results of attempted access for each mode.
To access the DMA identification and status registers in a privileged mode read CP15 with:
Opcode_1 set to 0
CRn set to c11
CRm set to c0
Opcode_2 set to:
0, Present
1, Queued
2, Running
3, Interrupting.
For example:
MRC p15, 0, <Rd>, c11, c0, 0 ; Read DMA Identification and Status Register present
MRC p15, 0, <Rd>, c11, c0, 1 ; Read DMA Identification and Status Register queued
MRC p15, 0, <Rd>, c11, c0, 2 ; Read DMA Identification and Status Register running
MRC p15, 0, <Rd>, c11, c0, 3 ; Read DMA Identification and Status Register interrupting.
3.2.34 c11, DMA User Accessibility Register
The purpose of the DMA User Accessibility Register is to determine if a User mode process can
access the registers for each channel.
The DMA User Accessibility Register is:
in CP15 c11
a 32-bit read/write register common to the Secure and Non-secure worlds
accessible in privileged modes only.
Figure 3-60 on page 3-108 shows the bit arrangement for the DMA User Accessibility Register.
2 Indicates channel running:
0 = the channel is not Running
1 = the channel is Running.
3 Indicates channel interrupting:
0 = the channel is not Interrupting
1 = the channel is Interrupting, through completion or an error.
4-7 Reserved. Results in an Undefined exception.
Table 3-105 DMA Identification and Status Register functions (continued)
Opcode_2 Function
Table 3-106 Results of access to the DMA identification and status registers
DMA bit
Secure Privileged Non-secure Privileged
User
Read Write Read Write
0 Data Undefined exception Undefined exception Undefined exception Undefined exception
1 Data Undefined exception Data Undefined exception Undefined exception

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