VFP Exception Handling
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-11
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In Example 22-3, FADDD is a short vector instruction with b011 in the LEN field for a vector
length of four iterations and b00 in the STRIDE field for a vector stride of one. It has a potential
Overflow exception in the first iteration, detected in cycle 4. The following FMACS is stalled in
the Decode stage. The FMACS is the trigger instruction and can be retried after exception
processing. FPINST2 is invalid and the FP2V flag is not set.
Example 22-3 Exceptional short vector FADDD with an FMACS trigger instruction
FADDD D4, D4, D12 ; Short vector double-precision add of length 4
FMACS S0, S3, S2 ; Scalar single-precision mac
Table 22-3 lists the pipeline stages for Example 22-3.
After exception processing begins, the FPEXC register fields contain the following:
EX 1 The VFP11 coprocessor is in the exceptional state.
EN 1
FP2V 0 FPINST2 does not contain a valid instruction.
VECITR 010 Three iterations remain.
INV 0
UFC 0
OFC 1 Exception detected is a potential overflow.
IOC 0
The FPINST register contains the FADDD instruction with the following fields modified to
reflect the register address of the first iteration:
Fd/D 0100/0 Destination of exceptional iteration is D4.
Fn/N 0100/0 Fn source of the first exceptional iteration is D4.
Fm/M 1100/0 Fm source of the first exceptional iteration is D12.
FPINST2 contains invalid data.
Table 22-3 Exceptional short vector FADDD with an FMACS trigger instruction
Instruction cycle number
Instruction 1 2 3 4 5678910111213141516
FADDD D4, D4, D12 D I E1 E2 ------------
FMACS S0, S3, S2 -DDI* --------
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