System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-36
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Table 3-27 lists the results of attempted access for each mode.
To use the Memory Model Feature Register 3 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c1
• Opcode_2 set to 7.
For example:
MRC p15, 0, <Rd>, c0, c1, 7 ;Read Memory Model Feature Register 3.
c0, Instruction Set Attributes Register 0
The purpose of the Instruction Set Attributes Register 0 is to provide information about the
instruction set that the processor supports beyond the basic set.
The Instruction Set Attributes Register 0 is:
•in CP15 c0
• a 32-bit read-only register common to the Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-21 shows the bit arrangement for Instruction Set Attributes Register 0.
Figure 3-21 Instruction Set Attributes Register 0 format
Table 3-28 lists how the bit values correspond with the Instruction Set Attributes Register 0
functions.
Table 3-27 Results of access to the Memory Model Feature Register 3
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Data Undefined exception Data Undefined exception Undefined exception
- - - - - -Reserved
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
-
Table 3-28 Instruction Set Attributes Register 0 bit functions
Bits Field name Function
[31:28] - Reserved. RAZ.
[27:24] - Indicates support for divide instructions.
0x0
, no support in ARM1176JZF-S processors.
[23:20] - Indicates support for debug instructions.
0x1
, ARM1176JZF-S processors support BKPT.
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