ARM ARM1176JZF-S User Manual

VFP Exception Handling
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-23
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22.12.5 FDIV
The thresholds for divide are simple and based only on the difference of the exponents of the
dividend and the divisor. It is not possible in a divide operation for the significand to overflow
and cause an increment of the exponent. However, it is possible for the significand to require a
single bit left shift and the exponent to be decremented for normalization. To reduce logic
complexity, the overflow ranges are the same as those of the LSA operations in FADD and
FSUB on page 22-20. The underflow ranges include the minimum normal exponent,
0x01 for
single-precision and
0x001 for double-precision. Table 22-10 lists the FDIV bounce thresholds.
The exponent values shown in Table 22-10 are in biased format.
22.12.6 FSQRT
It is not possible for FSQRT to overflow or underflow.
Table 22-10 FDIV bounce thresholds
Initial quotient exponent value
Float value
Condition in full-compliance mode
DP
a
a. DP = double-precision.
SP
b
b. SP = single-precision.
SP DP
>
0x7FF - DP overflow - Bounce
0x7FF - DP NaN or infinity - Bounce
0x7FE - DP maximum normal - Bounce
0x7FD - DP normal - Bounce
0x7FC - DP normal - Normal
>
0x47F > 0xFF SP overflow Bounce Normal
0x47F 0xFF SP NaN or infinity Bounce Normal
0x47E 0xFE SP maximum normal Bounce Normal
0x47D 0xFD SP normal Bounce Normal
0x47C 0xFC SP normal Normal Normal
0x3FF 0x7F e = 0 bias value Normal Normal
0x382 0x02 SP normal Normal Normal
0x381 0x01 SP normal Bounce Normal
0x380 0x00 SP subnormal Bounce Normal
<
0x380 < 0x00 SP underflow Bounce Normal
0x002 - DP normal - Normal
0x001 - DP normal - Bounce
0x000 - DP subnormal - Bounce
<
0x000 - DP underflow - Bounce

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English