Programmer’s Model
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-11
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Table 2-2 Secure Monitor bus signals
Bits Description
[24]
a
ETMIACTL[11] unmodified by Non-invasive security enable masking.
This signal is disabled when ETMPWRUP = 0 and the Performance Monitoring counters are disabled.
[23]
a
ETMIACTL[9] unmodified by Non-invasive security enable masking.
This signal is disabled when ETMPWRUP = 0 and the Performance Monitoring counters are disabled.
[22] Signal that indicates, for duration of operation, the execution of a DMB or DSB operation.
[21] Signal that indicates, for 1 cycle, the execution of a Prefetch Flush operation.
[20:19] Instruction/Unified TCM Region Register bit[0], entries [1:0].
[18:17] Data TCM Region Register bit [0], entries [1:0].
[16] Non-secure Access Control register bit [18].
[15] Secure Control Register I bit, bit [12].
[14] Secure Control Register C bit, bit [2].
[13] Secure Control Register M bit, bit [0].
[12] Secure Configuration Register NS bit, bit [0].
[11] CPSR A bit, bit [8], taken from the core pipeline writeback stage.
[10] CPSR I bit, bit [7], taken from the core pipeline writeback stage.
[9] CPSR F bit, bit [6], taken from the core pipeline writeback stage.
[8:5] CPSR mode bits, bits [3:0], taken from the core pipeline writeback stage.
[4:3] ETMDDCTL[1:0] unmodified by Non-invasive security enable masking.
This signal is disabled when ETMPWRUP = 0 and the Performance Monitoring counters are disabled.
[2:1]
a
ETMDACTL[1:0] unmodified by Non-invasive security enable masking.
This signal is disabled when ETMPWRUP = 0 and the Performance Monitoring counters are disabled.
[0]
a
ETMIACTL[0] unmodified by Non-invasive security enable masking.
This signal is disabled when ETMPWRUP = 0 and the Performance Monitoring counters are disabled.
a. nRESETIN resets all SECMONBUS output pins except bits [24:23] and bits [2:0].
nPORESETIN resets the output pins for bits [24:23] and bits [2:0].
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