System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-74
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Table 3-70 lists how the bit values correspond with the Cache Operation functions
for VA format operations.
You can perform invalidate, clean, and prefetch operations on:
• single cache lines
• entire caches
• address ranges in cache.
Note
• Clean, invalidate, and clean and invalidate operations apply regardless of the lock applied
to entries.
• An explicit flush of the relevant lines in the branch target cache must be performed after
invalidation of Instruction Cache lines or the results are Unpredictable. There is no impact
on security. This is not required after an entire Instruction Cache invalidation because the
entire branch target cache is flushed automatically.
• A small number of CP15 c7 operations can be executed by code while in User mode.
Attempting to execute a privileged operation in User mode using CP15 c7 results in an
Undefined instruction trap being taken.
To determine if the cache is dirty use the Cache Dirty Status Register, see Cache Dirty Status
Register on page 3-78.
Entire cache
Table 3-71 lists the instructions and operations that you can use to clean and
invalidate the entire cache.
Register c7 specifies operations for cleaning the entire Data Cache, and also for
performing a clean and invalidate of the entire Data Cache. These are blocking
operations that can be interrupted. If they are interrupted, the R14 value that is
Table 3-70 Functional bits of c7 for VA format
Bits Field name Function
[31:5] Virtual address Specifies the start or end address to invalidate or clean.
Holds the true VA of the start or end of a memory block before any modification by FCSE.
[4:0] - SBZ.
Table 3-71 Cache operations for entire cache
Instruction Data Function
MCR p15, 0, <Rd>, c7, c5, 0
SBZ Invalidate Entire Instruction Cache.
Also flushes the branch target cache and globally flushes the BTAC.
MCR p15, 0, <Rd>, c7, c6, 0
SBZ Invalidate Entire Data Cache.
MCR p15, 0, <Rd>, c7, c7, 0
SBZ Invalidate Both Caches.
Also flushes the branch target cache and globally flushes the BTAC.
MCR p15, 0, <Rd>, c7, c10, 0
SBZ Clean Entire Data Cache.
MCR p15, 0, <Rd>, c7, c14, 0
SBZ Clean and Invalidate Entire Data Cache.
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