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Level Two Interface

ID012310 Non-Confidential, Unrestricted Access

AxSIDEBAND[4:0]

The AxSIDEBAND[4:1] signals indicate the bufferable, cacheable, write-through, write-back,

and allocate attributes of the level one memory. AxSIDEBAND[0] indicates the Shared

attribute. Table 8-8 shows the correspondence between the AxSIDEBAND[4:1] encoding and

the TLB cacheable attributes for the Read/Write, Peripheral, and DMA ports.

Table 8-9 shows the correspondence between the ARSIDEBANDI[4:1] encoding and the TLB

cacheable attributes for the Instruction port.

These signals are not part of the AXI protocol and are added for additional information.

Table 8-8 AxSIDEBAND[4:1] encoding

AxSIDEBAND[4:1] Transaction attributes

b0000 Strongly ordered

b0001 Shared device or non-shared device

b0010 Inner noncacheable

b0110 Inner write-through, no allocate on write

b0111 Inner write-back, no allocate on write

b1111

Inner write-back, write allocate

a. The ARM1176JZF-S processor does not support write allocate.

Table 8-9 ARSIDEBANDI[4:1] encoding

ARSIDEBANDI[4:1] Transaction attributes

b0000 Strongly Ordered

b0001 Device

b0010 Inner Noncacheable

b0110 Inner Cacheable

ARM ARM1176JZF-S User Manual

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