ARM ARM1176JZF-S - Table 8-21 Noncacheable LDM4, Strongly Ordered or Device Memory; Table 8-22 Noncacheable LDM4, Noncacheable Memory or Cache Disabled; Noncacheable LDM4 from Word 5, 6, or 7

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• Table 8-22 for a load from Noncacheable memory or when the cache is disabled.
A Noncacheable LDM4 addressing words 5 to 7 is split into two operations as shown in
Table 8-23.
8.5.8 Noncacheable LDM5
The values of ARADDRRW, ARBURSTRW, ARSIZERW, and ARLENRW for
Noncacheable LDM5s addressing words 0 to 3 are shown in:
• Table 8-24 on page 8-20 for a load from Strongly Ordered or Device memory
• Table 8-25 on page 8-20 for a load from Noncacheable memory or when the cache is
disabled.
Table 8-21 Noncacheable LDM4, Strongly Ordered or Device memory
Address[4:0] ARADDRRW ARBURSTRW ARSIZERW ARLENRW
0x00 , word 0 0x00 Incr 64-bit 2 data transfers
0x04 , word 1 0x04 Incr 32-bit 4 data transfers
0x08 , word 2 0x08 Incr 64-bit 2 data transfers
0x0C , word 3 0x0C Incr 32-bit 4 data transfers
0x10 , word 4 0x10 Incr 64-bit 2 data transfers
Table 8-22 Noncacheable LDM4, Noncacheable memory or cache disabled
Address[4:0] ARADDRRW ARBURSTRW ARSIZERW ARLENRW
0x00 , word 0 0x00 Incr 64-bit 2 data transfers
0x04 , word 1 0x04 Incr 64-bit 3 data transfers
0x08 , word 2 0x08 Incr 64-bit 2 data transfers
0x0C , word 3 0x0C Incr 64-bit 3 data transfers
0x10 , word 4 0x10 Incr 64-bit 2 data transfers
Table 8-23 Noncacheable LDM4 from word 5, 6, or 7
Address[4:0] Operations
0x14 , word 5 LDM3 from 0x14 + LDR from 0x00
0x18
, word 6 LDM2 from 0x18 + LDM2 from 0x00
0x1C
, word 7 LDR from 0x1C + LDM3 from 0x00