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Cycle Timings and Interlock Behavior

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16.5 ARMv6 media data-processing

Table 16-7 lists ARMv6 media data-processing instructions and gives their cycle timing

behavior.

All ARMv6 media data-processing instructions are single-cycle issue instructions. These

instructions produce their results in either the ALU or Sat stage, and have result latencies of one

or two accordingly. Some of the instructions require an input register to be shifted before use

and therefore are marked as requiring an Early Reg.

Table 16-7 ARMv6 media data-processing instructions cycle timing behavior

Instructions

Cycle

Early Reg Result latency

SADD16, SSUB16, SADD8, SSUB8 1 - 1

USAD8, USADA8 1

UADD16, USUB16, UADD8, USUB8 1 - 1

SEL 1 - 1

QADD16, QSUB16, QADD8, QSUB8 1 - 2

SHADD16, SHSUB16, SHADD8, SHSUB8 1 - 2

UQADD16, UQSUB16, UQADD8, UQSUB8 1 - 2

UHADD16, UHSUB16, UHADD8, UHSUB8 1 - 2

SSAT16, USAT16 1 - 2

SADDSUBX, SSUBADDX 1

<Rm>

UADDSUBX, USUBADDX 1

<Rm>

SADD8TO16, SADD8TO32, SADD16TO32 1

<Rm>

SUNPK8TO16, SUNPK8TO32, SUNPK16TO32 1

<Rm>

UUNPK8TO16, UUNPK8TO32, UUNPK16TO32 1

<Rm>

UADD8TO16, UADD8TO32, UADD16TO32 1

<Rm>

REV, REV16, REVSH 1

<Rm>

PKHBT, PKHTB 1

<Rm>

SSAT, USAT 1

<Rm>

QADDSUBX, QSUBADDX 1

<Rm>

SHADDSUBX, SHSUBADDX 1

<Rm>

UQADDSUBX, UQSUBADDX 1

<Rm>

UHADDSUBX, UHSUBADDX 1

<Rm>

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English

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