System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-92
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Table 3-87 lists how the bit values correspond with the Instruction TCM Region Register
functions.
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
The value of the En bit at Reset depends on the INITRAM signal:
• INITRAM LOW sets En to 0
• INITRAM HIGH sets En to 1.
When INITRAM is HIGH this enables the Instruction TCM directly from reset, with a Base
address of
0x00000
. When the processor comes out of reset, it executes the instructions in the
Instruction TCM instead of fetching instructions from external memory, except when the
processor uses high vectors.
Note
When the NS access bit is 0 for Instruction TCM, see c9, Instruction TCM Non-secure Control
Access Register on page 3-94, attempts to access the Instruction TCM Region Register from the
Non-secure world cause an Undefined exception.
Table 3-87 Instruction TCM Region Register bit functions
Bits
Field
name
Function
[31:12] Base
address
Contains the physical base address of the TCM. The base address must be aligned to the size of the
TCM. Any bits in the range [(log
2
(RAMSize)-1):12] are ignored.
The base address is 0 at Reset.
[11:7] - UNP/SBZ.
[6:2] Size
Indicates the size of the TCM on reads
a
. All other values are reserved:
b00000 = 0KB
b00011 = 4KB
b00100 = 8KB
b00101 = 16KB
b00110 = 32KB.
[1] - UNP/SBZ.
[0] En Indicates if the TCM is enabled:
0 = TCM disabled.
1 = TCM enabled.
The reset value of this bit depends on the value of the INITRAM static configuration signal. If
INITRAM is HIGH then this bit resets to 1. If INITRAM is LOW then this bit resets to 0. For more
information see Static configuration signals on page A-4.
a. On writes this field is ignored. For more details see Tightly-coupled memory on page 7-7.
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