VFP Programmer’s Model
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 20-3
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20.2 Compliance with the IEEE 754 standard
This section introduces issues related to compliance with the IEEE 754 standard:
• hardware and software components
• software-based components and their availability.
Also see Section C1 of the ARM Architecture Reference Manual for information about VFP
architecture compliance with the IEEE 754 standard.
20.2.1 An IEEE 754 standard-compliant implementation
The VFP11 hardware and support code together provide VFPv2 floating-point instruction
implementations that are compliant with the IEEE 754 standard. Unless an enabled
floating-point exception occurs, it appears to the program that the floating-point instruction was
executed by the hardware. If an exceptional condition occurs that requires software support
during instruction execution, the instruction takes significantly more cycles than normal to
produce the result. This is a common practice in the industry, and the incidence of such
instructions is typically very low.
20.2.2 Complete implementation of the IEEE 754 standard
The following operations from the IEEE 754 standard are not supplied by the VFP11 instruction
set:
• remainder
• round floating-point number to integer-valued floating-point number
• binary-to-decimal conversions
• decimal-to-binary conversions
• direct comparison of single-precision and double-precision values.
For complete implementation of the IEEE 754 standard, the VFP11 coprocessor and support
code must be augmented with library functions that implement these operations. See
Application Note 98, VFP Support Code for details of support code and the available library
functions.
20.2.3 IEEE 754 standard implementation choices
Part C of the ARM Architecture Reference Manual describes some of the implementation
choices permitted by the IEEE 754 standard and used in the VFPv2 architecture.
Additional implementation choices are made within the VFP11 coprocessor about the cases that
are handled by the VFP11 hardware and the cases that bounce to the support code.
To execute frequently encountered operations as fast as possible and minimize silicon area,
handling of rarely occurring values and some exceptions is relegated to the support code. The
VFP11 coprocessor supports two modes for handling rarely occurring values:
Full-compliance mode
Full-compliance mode with support code assistance is fully compliant with the
IEEE 754 standard. Full-compliance mode requires the floating-point support
code to handle certain operands and exceptional conditions not supported in the
hardware. Although the support code gives full compliance with the IEEE 754
standard, it does increase the runtime of an application and the size of kernel code.
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