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Programmer’s Model

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Note

An attempt by a User process to execute an SMC makes the processor enter the Undefined

exception trap.

2.12.14 Undefined instruction

When an instruction is encountered that neither the processor, nor any coprocessor in the

system, can handle the processor takes the undefined instruction trap. Software can use this

mechanism to extend the ARM instruction set by emulating undefined coprocessor instructions.

After emulating the failed instruction, the trap handler executes the following instruction,

irrespective of the processor operating state:

MOVS PC,R14_und

This action restores the CPSR and returns to the next instruction after the undefined instruction.

IRQs are disabled when an undefined instruction trap occurs. For more information about

undefined instructions, see the ARM Architecture Reference Manual.

2.12.15 Breakpoint instruction (BKPT)

A breakpoint (BKPT) instruction operates as though the instruction causes a Prefetch Abort.

A breakpoint instruction does not cause the processor to take the Prefetch Abort exception until

the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for

example because a branch occurs while it is in the pipeline, the breakpoint does not take place.

After dealing with the breakpoint, the handler executes the following instruction irrespective of

the processor operating state:

SUBS PC,R14_abt,#4

This action restores both the PC and the CPSR, and retries the breakpointed instruction.

Note

If the EmbeddedICE-RT logic is configured into Halting debug-mode, a breakpoint instruction

causes the processor to enter Debug state. See Halting debug-mode debugging on page 13-50.

2.12.16 Exception vectors

The Secure Configuration Register bits [3:1] determine the mode that is entered when an IRQ,

a FIQ, or an external abort exception occur.

Three CP15 registers define the base address of the following vector tables:

• Non-secure, Non_Secure_Base_Address

• Secure, Secure_Base_Address

• Secure Monitor, Monitor_Base_Address.

If high vectors are enabled, Non_Secure_Base_Address and Secure_Base_Address registers are

treated as being

0xFFFF0000

, regardless of the value of these registers.

Exceptions occurring in Non-secure world

The following exceptions occur in the Non-secure world:

• Reset on page 2-49

ARM ARM1176JZF-S User Manual

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