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Trace Interface Port

ID012310 Non-Confidential, Unrestricted Access

In these cases, if an exception occurs before the first instruction is traced, an additional

placeholder instruction is traced. The placeholder instruction is followed immediately by a

branch packet that indicates the type of exception. This exception is marked as a canceling

exception, to indicate that the placeholder instruction was not executed. The instruction at the

exception vector is then traced, and trace continues as normal.

This extra instruction cannot be generated on a reset exception. Therefore, if the processor exits

Debug state or a prohibited region because of a reset, trace does not report a reset exception.

For more information on the ETM protocol, see the Embedded Trace Macrocell Architecture

Specification.

15.1.2 Secure control bus

The Secure control bus ETMIASECCTL indicates when the processor is in Secure state and

when the data trace is prohibited.

Table 15-3 lists the signals in the Secure control bus ETMIASECCTL.

15.1.3 Data address interface

Data addresses are sampled at the ADD stage because they are guaranteed to be in order at this

point. These are assigned a slot number for identification on retirement.

Table 15-4 lists the data address interface signals.

Table 15-3 ETMIASECCTL[1:0]

Bits Reference name Description Qualified by

[1] IASProhibited Trace prohibited for this instruction IAValid

[0] IASNonSecure Instruction executed in Non-secure state IAValid

Table 15-4 Data address interface signals

Signal name Description Qualified by

ETMDACTL[17:0

]

Data address interface control signals -

ETMDA[31:3] Address for data transfer DASlot != 00 AND !DACPRT

ARM ARM1176JZF-S User Manual

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