System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-19
ID012310 Non-Confidential, Unrestricted Access
Table 3-3 lists the operations available with MCRR operations:
MCRR{cond} P15,<Opcode_1>,<End Address>,<Start Address>,<CRm>
b. Reset value depends on the cache size implemented. The value here is for 16KB instruction and data caches.
c. Reset value depends on the number of TCM banks implemented. The value here is for 2 data TCM and 2 instruction TCM
banks.
d. Some bits in this register are banked and some Secure modify only.
e. Reset value depends on external signals.
f. Reset value depends on the TCM sizes implemented. The value here is for 16KB TCM banks.
g. Reset value depends on the TCM sizes implemented, and on the value of the INITRAM static configuration signal. The value
here is for 16KB TCM banks, with INITRAM tied LOW.
h. Some bits in this register are common and some Secure modify only.
i. Reset value depends on the number of DMA channels implemented and the presence of TCMs.
j. Reset value depends on external signals.
k. This register is read/write in Privileged modes and read-only on User mode.
l. Reset value depends on the cache and TCM sizes implemented. The value here is for 2 banks of 16KB instruction and data
TCMs and 16KB instruction and data caches.
Table 3-3 Summary of CP15 MCRR operations
Op1 CRm Register or operation S type NS type Reset value Page
0 c5 Invalidate instruction cache range WO WO - page 3-69
c6 Invalidate data cache range WO WO - page 3-69
c12 Clean data cache range WO WO -page3-69
c14 Clean and invalidate data cache range WO WO - page 3-69
To Next Page
Loading...
Need help?
General
