ARM ARM1176JZF-S User Manual

System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-18
ID012310 Non-Confidential, Unrestricted Access
c13 0 c0 0 FCSE PID R/W, B, X R/W 0x00000000 page 3-126
1 Context ID R/W, B R/W
0x00000000 page 3-128
2 User Read/Write Thread and
Process ID
R/W, B R/W
0x00000000 page 3-129
3 User Read-only Thread and
Process ID
R/W, RO,
B
k
R/W,
RO
0x00000000 page 3-129
4 Privileged Only Thread and
Process ID
R/W, B R/W 0x00000000 page 3-129
c14 Not used
c15 0 c2 4 Peripheral Port Memory
Remap
R/W, B, X R/W 0x00000000 page 3-130
c9 0 Secure User and Non-secure
Access Validation Control
R/W, X NA
0x00000000 page 3-132
c12 0 Performance Monitor Control R/W, X R/W, X
0x00000000 page 3-133
1 Cycle Counter R/W, X R/W, X
0x00000000 page 3-137
2 Count 0 R/W, X R/W, X
0x00000000 page 3-138
3 Count 1 R/W, X R/W, X
0x00000000 page 3-139
4-7 System Validation Counter R/W, X R/W, X
0x00000000 page 3-140
c13 1-7 System Validation Operations R/W, X R/W, X
0x00000000 page 3-142
c14 0 System Validation Cache Size
Mask
R/W, X R/W, X
0x00006655
l
page 3-145
c15 1 c13 0-7 System Validation Operations R/W, X R/W, X
0x00000000 page 3-142
c15 2 c13 1-7 System Validation Operations R/W, X R/W, X
0x00000000 page 3-142
c15 3 c8 0-7 Instruction Cache Master Valid R/W, X NA
0x00000000 page 3-147
c12 0-7 Data Cache Master Valid R/W, X NA
0x00000000 page 3-148
c13 0-7 System Validation Operations R/W, X R/W, X
0x00000000 page 3-142
c15 4 c13 0-7 System Validation Operations R/W, X R/W, X
0x00000000 page 3-142
c15 5 c4 2 TLB Lockdown Index R/W, X NA
0x00000000 page 3-149
c5 2 TLB Lockdown VA R/W, X NA - page 3-149
c6 2 TLB Lockdown PA R/W, X NA - page 3-149
c7 2 TLB Lockdown Attributes R/W, X NA - page 3-149
c13 0-7 System Validation Operations R/W, X R/W, X
0x00000000 page 3-142
c15 6 c13 0-7 System Validation Operations R/W, X R/W, X
0x00000000 page 3-142
c15 7 c13 0-7 System Validation Operations R/W, X R/W, X
0x00000000 page 3-142
a. See c0, Main ID Register on page 3-20 for the values of bits [23:20] and bits [3:0].
Table 3-2 Summary of CP15 registers and operations (continued)
CRn Op1 CRm Op2 Register or operation S type
NS
type
Reset
value
Page

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English