System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-134
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Table 3-136 lists how the bit values correspond with the Performance Monitor Control Register.
Table 3-136 Performance Monitor Control Register bit functions
Bits Field name Function
[31:28] - UNP/SBZ.
[27:20] EvtCount0 Identifies the source of events for Count Register 0.
Table 3-137 on page 3-135 lists the values, functions and EVNTBUS bit position for Count
Register 0. The reset value is 0.
[19:12] EvtCount1 Identifies the source of events for Count Register 1.
Table 3-137 on page 3-135 lists the values and the bit functions for Count Register 1. The reset
value is 0.
[11] X Enable Export of the events to the event bus to an external monitoring block, such as the ETM
to trace events:
0 = Export disabled, EVNTBUS held at
0x0
, reset value
1 = Export enabled, EVNTBUS driven by the events.
[10] CCR Cycle Counter Register overflow flag:
0 = For reads No overflow, reset value.
For writes No effect.
1 = For reads, overflow occurred.
For writes Clear this bit.
[9] CR1 Count Register 1 overflow flag:
0 = For reads No overflow, reset value.
For writes No effect.
1 = For reads, overflow occurred.
For writes Clear this bit.
[8] CR0 Count Register 0 overflow flag:
0 = For reads No overflow, reset value.
For writes No effect.
1 = For reads overflow occurred.
For writes Clear this bit.
[7] - UNP/SBZ.
[6] ECC Used to enable and disable Cycle Counter interrupt reporting:
0 = Disable interrupt, reset value
1 = Enable interrupt.
[5] EC1 Used to enable and disable Count Register 1 interrupt reporting:
0 = Disable interrupt, reset value
1 = Enable interrupt.
[4] EC0 Used to enable and disable Count Register 0 interrupt reporting:
0 = Disable interrupt, reset value
1 = Enable interrupt.
[3] D Cycle count divider:
0 = Counts every processor clock cycle, reset value
1 = Counts every 64th processor clock cycle.
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