ARM ARM1176JZF-S User Manual

Level Two Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-18
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8.5.6 Noncacheable LDM3
The values of ARADDRRW, ARBURSTRW, ARSIZERW, and ARLENRW for
Noncacheable LDM3s addressing words 0 to 5 are shown in:
• Table 8-18 for a load from Strongly Ordered or Device memory
• Table 8-19 for a load from Noncacheable memory or when the cache is disabled.
A Noncacheable LDM3 addressing word 6 or 7 is split into two operations as shown in
Table 8-20.
8.5.7 Noncacheable LDM4
The values of ARADDRRW, ARBURSTRW, ARSIZERW, and ARLENRW for
Noncacheable LDM4s addressing words 0 to 4 are shown in:
• Table 8-21 on page 8-19 for a load from Strongly Ordered or Device memory
Table 8-17 Noncacheable LDRD or LDM2 from word 7
Address[4:0] Operations
0x1C , word 7 LDR from 0x1C + LDR from 0x00
Table 8-18 Noncacheable LDM3, Strongly Ordered or Device memory
Address[4:0] ARADDRRW ARBURSTRW ARSIZERW ARLENRW
0x00 , word 0 0x00 Incr 32-bit 3 data transfers
0x04 , word 1 0x04 Incr 32-bit 3 data transfers
0x08 , word 2 0x08 Incr 32-bit 3 data transfers
0x0C , word 3 0x0C Incr 32-bit 3 data transfers
0x10 , word 4 0x10 Incr 32-bit 3 data transfers
0x14 , word 5 0x14 Incr 32-bit 3 data transfers
Table 8-19 Noncacheable LDM3, Noncacheable memory or cache disabled
Address[4:0] ARADDRRW ARBURSTRW ARSIZERW ARLENRW
0x00 , word 0 0x00 Incr 64-bit 2 data transfers
0x04 , word 1 0x04 Incr 64-bit 2 data transfers
0x08 , word 2 0x08 Incr 64-bit 2 data transfers
0x0C , word 3 0x0C Incr 64-bit 2 data transfers
0x10 , word 4 0x10 Incr 64-bit 2 data transfers
0x14 , word 5 0x14 Incr 64-bit 2 data transfers
Table 8-20 Noncacheable LDM3 from word 6, or 7
Address[4:0] Operations
0x18 , word 6 LDM2 from 0x18 + LDR from 0x00
0x1C
, word 7 LDR from 0x1C + LDM2 from 0x00

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English