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Debug Test Access Port

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14.3 Entering Debug state

Halting debug-mode is enabled by writing a 1 to bit 14 of the DSCR, see CP14 c1, Debug Status

and Control Register (DSCR) on page 13-7. This can only be done by a DBGTAP debugger

hardware such as RealView ICE. When this mode is enabled and the core is in a state where

debug is permitted the processor halts, instead of taking an exception in software, if one of the

following events occurs:

• vector catch occurs

• a breakpoint hits

• a watchpoint hits

• a BKPT instruction is executed.

The processor also enters Debug state, provided that its state permits debug, when:

• A Halt instruction has been scanned in through the DBGTAP. The DBGTAP controller

must pass through Run-Test/Idle to issue the Halt command to the processor.

• EDBGRQ is asserted.

If debug is enabled by DBGEN, scanning a Halt instruction in through the DBGTAP, or

asserting EDBGRQ, halts the processor and causes it to enter Debug state, regardless of the

selection of a debug-state in DSCR[15:14]. This means that a debugger can halt the processor

immediately after reset in a situation where it cannot first enable Halting debug-mode during

reset.

The core halted bit in the DSCR is set when Debug state is entered. At this point, the debugger

determines why the integer core was halted and preserves the processor state. The MSR

instruction can be used to change modes permitted by the SPIDEN signal and SUIDEN bit and

gain access to banked registers in the machine. While in Debug state:

• the PC is not incremented

• interrupts are ignored

• all instructions are read from the instruction transfer register, scan chain 4.

Debug state on page 13-37 describes the Debug state.

ARM ARM1176JZF-S User Manual

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