System Control Coprocessor
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• Prefetch code into the Instruction cache.
The terms used to describe the invalidate, clean, and prefetch operations are as defined in the
Caches and Write Buffers chapter of the ARM Architecture Reference Manual.
For details of the behavior of c7 in the Secure and Non-secure worlds, see TrustZone behavior
on page 3-77.
When it controls invalidate, clean, and prefetch operations c7 appears as a 32-bit write only
register. There are four possible formats for the data that you write to the register that depend on
the specific operation:
• Set and Index format
•MVA
•VA
•SBZ.
Set and Index format
Figure 3-40 shows the Set and Index format for invalidate and clean operations.
Figure 3-40 c7 format for Set and Index
Table 3-67 lists how the bit values correspond with the Cache Operation functions
for Set and Index format operations.
The value of S in Table 3-68 depends on the cache size. Table 3-68 lists the
relationship of cache sizes and S.
0Set
31
30
29 S+5 1 0
SBZ/UNP Index SBZ/UNP
45S+4
Table 3-67 Functional bits of c7 for Set and Index
Bits Field name Function
[31:30] Set Selects the cache set to operate on, from the four cache sets.
Value is the cache set number.
[29:S+5] - UNP/SBZ.
[S+4:5] Index Selects the cache line to operate on.
Value is the index number.
[4:1] - SBZ.
[0] 0 For the ARM1176JZF-S, this Should Be Zero.
Table 3-68 Cache size and S parameter dependency
Cache size S
4KB 5
8KB 6
16KB 7
32KB 8
64KB 9
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