ARM ARM1176JZF-S - Table 3-111 Results of Access to the DMA Enable Registers

System Control Coprocessor
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• the interrupt that is set by the DMA channel as a result of an error or
completion, see c11, DMA Control Register on page 3-112 for more details.
The Clear command does not change the contents of the Internal and External
Start Address Registers. A Clear command has no effect when the channel status
is Running or Queued.
Access in the Non-secure world depends on the DMA bit, see c1, Non-Secure Access Control
Register on page 3-55. The processor can access these registers in User mode if the U bit, see
c11, DMA User Accessibility Register on page 3-107, for the currently selected channel is set to
1. Table 3-111 lists the results of attempted access for each mode.
To access a DMA Enable Register set the DMA Channel Number Register to the appropriate
DMA channel and write CP15 with:
• Opcode_1 set to 3
• CRn set to c11
• CRm set to c3
• Opcode_2 set to:
—0, Stop
—1, Start
—2, Clear.
For example:
MCR p15, 0, <Rd>, c11, c3, 0 ; Stop DMA Enable Register
MCR p15, 0, <Rd>, c11, c3, 1 ; Start DMA Enable Register
MCR p15, 0, <Rd>, c11, c3, 2 ; Clear DMA Enable Register
Debug implications for the DMA
The level one DMA behaves as a separate engine from the processor core, and when started,
works autonomously. When the level one DMA has channels with the status of Running or
Queued, these channels continue to run, or start running, even if a debug mechanism stops the
processor. This can cause the contents of the TCM to change while the processor stops in debug.
To avoid this situation you must ensure the level one DMA issues a Stop command to stop
Running or Queued channels when entering debug.
Table 3-111 Results of access to the DMA enable registers
U
bit
DMA
bit
Secure
Privileged
Non-secure
Privileged
Secure User Non-secure User
Read Write Read Write Read Write Read Write
0 0 Undefined
exception
Data Undefined
exception
Undefined
exception
Undefined
exception
Undefined
exception
Undefined
exception
Undefined
exception
1 Undefined
exception
Data Undefined
exception
Data Undefined
exception
Undefined
exception
Undefined
exception
Undefined
exception
1 0 Undefined
exception
Data Undefined
exception
Undefined
exception
Undefined
exception
Data Undefined
exception
Undefined
exception
1 Undefined
exception
Data Undefined
exception
Data Undefined
exception
Data Undefined
exception
Data