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Introduction

ID012310 Non-Confidential, Unrestricted Access

The TCM can be anywhere in the memory map. The INITRAM pin enables booting from the

ITCM.

See Chapter 7 Level One Memory System for more details.

TCM DMA engine

To support use of the TCMs by data-intensive applications, the core provides two DMA

channels to transfer data to or from the Instruction or Data TCM blocks. DMA can proceed in

parallel with CPU accesses to the TCM blocks. Arbitration is on a cycle-by-cycle basis. The

DMA channels connect with the System-on-Chip (SoC) backplane through a dedicated 64-bit

AMBA AXI port.

The DMA controller is programmed using the CP15 system-control coprocessor. DMA accesses

can only be to or from the TCM, and an external memory. There is no coherency support with

the caches.

Note

Only one of the two DMA channels can be active at any time.

DMA features

The DMA controller has the following features:

• runs in background of CPU operations

• enables CPU priority access to TCM during DMA

• programmed with Virtual Addresses

• controls DMA to either the instruction or data TCM

• allocated by a privileged process (OS)

• software can check and monitor DMA progress

• interrupts on DMA event

• ability to configure each channel to transfer data between Secure TCM and Secure

external memory.

Memory Management Unit

The Memory Management Unit (MMU) has a unified Translation Lookaside Buffer (TLB) for

both instructions and data. The MMU includes a 4KB page mapping size to enable a smaller

RAM and ROM footprint for embedded systems and operating systems such as WindowsCE

that have many small mapped objects. The ARM1176JZF-S processor implements the Fast

Context Switch Extension (FCSE) and high vectors extension that are required to run Microsoft

WindowsCE. See Chapter 6 Memory Management Unit for more details.

16KB 2 8KB

32KB 2 16KB

64KB 2 32KB

Table 1-1 TCM configurations (continued)

Configured TCM size Number of TCMs Size of each TCM

ARM ARM1176JZF-S User Manual

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