Debug
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-16
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13.3.7 CP14 c64-c69, Breakpoint Value Registers (BVR)
Table 13-8 lists the Breakpoint Value Registers that the processor implements.
Each BVR is associated with a BCR register. BCRy is the corresponding control register for
BVRy.
A pair of breakpoint registers, BVRy/BCRy, is called a Breakpoint Register Pair (BRP).
BVR0-5 are paired with BCR0-5 to make BRP0-5.
The BVR of a BRP is loaded with an IMVA and then its contents can be compared against the
IMVA bus of the processor. The breakpoint value contained in the BVR corresponds to either
an IMVA or a context ID. Breakpoints can be set on:
•an IMVA
•a context ID
• an IMVA/context ID pair.
The IMVA comparison can be programmed to either hit when the address matches or
mis-matches. The IMVA mis-match case is useful because it enables a debugger to implement
a single-step operation when the breakpoint is programmed to match any other IMVA than the
instruction about to be executed.
The processor supports thread-aware breakpoints and watchpoints. A context ID can be loaded
into the BVR and the BCR can be configured so this BVR value is compared against the CP15
Context ID Register, c13, instead of the IMVA bus. Another register pair loaded with an IMVA
or DMVA can then be linked with the context ID holding BRP. A breakpoint or watchpoint
debug event is only generated if both the address and the context ID match at the same time.
This means that unnecessary hits can be avoided when debugging a specific thread within a task.
Breakpoint debug events generated on context ID matches only are also supported. However, if
a context ID only match or any match including an IMVA mis-match occurs while the processor
is running in a privileged mode and the debug logic in Monitor debug-mode, it is ignored. This
is to avoid the processor ending in an unrecoverable state.
VCR[30] = 1 NS bit = 1 and mode ≠ Secure
Monitor
00 NSBA +
0x00000018
1
0xFFFF0018
1 X Most recent Non-secure IRQ address.
VCR[31] = 1 NS bit = 1 and mode ≠ Secure
Monitor
X0 NSBA +
0x0000001C
1
0xFFFF001C
Table 13-7 Summary of debug entry and exception conditions (continued)
VCR bit NS bit, mode VE HIVECS Prefetch vector
Table 13-8 Processor breakpoint and watchpoint registers
Binary address
Register
number
CP14 debug register name Abbreviation
Context ID
capable?
Opcode_2 CRm
b100 b0000-b0011 c64-c67 Breakpoint Value Registers 0-3 BVR0-3 No
b0100-b0101 c68-c69 Breakpoint Value Registers 4-5 BVR4-5 Yes
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